Known types of Schmitt trigger input buffer circuits include one which uses a combination of CMOS inverters and a resistor, one which uses a R-S flip-flop comprising two NOR gates or two NAND gates, and one which uses three or more NAND gates.
An example of Schmitt trigger input buffer circuit using CMOS inverters and a resistor is shown in FIG. 6 of Japanese Unexamined Patent Publication No. SHO 62-292014 published on Dec. 18, 1987. The Schmitt trigger input buffer circuit of this type includes three inverters connected in series with an input terminal, a resistor connected in parallel with the series combination of the second and third inverters, and an output terminal connected to the output of the second inverter. A resistor may be substituted for the first inverter. Further, an inverting output terminal may be connected to the output of the third inverter. This type of Schmitt trigger input buffer circuit has disadvantages since the adjustment of its hysteresis characteristic is not easy and its input impedance cannot be large.
The second one of the above-mentioned types of Schmitt trigger input buffer circuits, which includes a R-S flip-flop employing NOR gates, is shown, for example, in FIG. 7 of Japanese Unexamined Patent Publication No. HEI 1-123517 published on May 16, 1989. An example of this type of Schmitt trigger input buffer circuit is shown in accompanying FIG. 1. The circuit of FIG. 1 includes an input terminal 1, a first input gate 2 comprising an inverting gate, a second input gate 3 comprising an inverting gate, an output terminal 4, and a third input gate 9 which is connected in series with the second input gate 3 and which comprises an inverting gate. The circuit further includes a first NOR gate 10 having two input terminals 10a and 10b, and a second NOR gate 11 having two input terminals 11a and 11b. In the above-cited Japanese Unexamined Patent Publication No. HEI 1-123517, a dual inverting input AND gate is used in place of the NOR gate 10, but its function is the same as that of NOR gate 10. The first and second NOR gates 10 and 11 form a R-S flip-flop 30.
An input signal SIN is applied at the input terminal 1 and coupled through two signal paths which respectively include the input gate 2, and the series combination of the input gates 3 and 9, to the R-S flip-flop circuit 30, as two inputs which are inverted with respect to each other. In the illustrated example, in FIG. 1, the input terminals 10a and 11b of the respective NOR gates 10 and 11 provide input terminals of R-S flip-flop circuit 30. An output signal SOUT is derived from an output terminal of R-S flip-flop circuit 30 or terminal 4, which is an output of the NOR gate 10.
In the R-S flip-flop 30, one input terminal 10a of the NOR gate 10 is connected to the output of the input gate 2, as stated above, and the other input terminal 10b of the NOR gate 10 is connected to the output of the NOR gate 11. One input terminal 11a of the NOR gate 11 is connected to the output of the NOR gate 10, and the other input terminal 11b is connected to the output of the input gate 9.
In the Schmitt trigger input buffer circuit with the above-described structure, a SET signal (not shown) having the same logic value (1 or 0) as the input signal SIN is applied from the input gate 9, a RESET signal (not shown) having a different logic value (0 or 1) is applied from the input gate 2, and, therefore, the output signal SOUT, having the same logic value as the input signal SIN, is developed at the output terminal 4. Hysteresis is provided for the output signal SOUT with respect to the input signal SIN by setting different threshold voltages VT2 and VT3 for the input gates 2 and 3, respectively.
Now, the operation of this Schmitt trigger input buffer circuit, when the amplitude of the input signal SIN applied to the input terminal 1 rises from the ground potential GND to a supply potential VDD, is explained.
When the input terminal 1 is at the ground potential GND, the outputs of the input gates 2 and 3 are at the supply potential VDD. Thus, the output of the third input gate 9 is at the ground potential GND. The first NOR gate 10 to which the output at the ground potential GND of the first input gate 2 is applied develops the ground potential GND as its output. The second NOR gate 11 receives the output value, i.e. the ground potential GND, of the third input gate 9, and also the output value, i.e. the ground potential GND, of the first NOR gate 10, and develops the supply potential VDD as its output.
As stated previously, input gates 2 and 3 have operating threshold values VT2 and VT3, respectively. Let it be assumed that VT2&lt;VT3. When the input signal voltage SIN increases and a condition in which VT3&gt;SIN&gt;VT2 occurs, the output of the first input gate 2 is inverted to the ground potential GND. However, since the output of the NOR gate 11 remains at the supply potential VDD, no change occurs in the outputs of the NOR gates 10 and 11.
When the input signal SIN further increases to a value above the threshold voltage VT3 of the second input gate 3, the outputs of the input gates 3 and 9 are inverted so that the ground potential GND and the supply potential VDD are respectively developed. The second NOR gate 11 receives the supply potential VDD which is the output of the input gate 9, and develops the ground potential GND as its output. Therefore, first NOR gate receives the output GND from the NOR gate 11 and the output GND from the first input gate 2, and develops the supply potential VDD at its output.
Next, the operation in which the voltage of the input signal SIN at the input terminal 1 changes from the supply potential VDD down to the ground potential GND, is considered.
When the input terminal 1 is at the supply potential VDD, the outputs of both input gates 2 and 3 are at the ground potential GND. Accordingly, the output of the third gate 9 is at the supply potential VDD. This output of gate 9 causes the second NOR gate 11 to develop an output at the ground potential GND. The first NOR gate 10 receives the output at the ground potential GND of the input gate 2 and the output potential GND of the second NOR gate 11, and develops an output at the supply potential VDD as its output.
When the input signal SIN decreases and becomes below the lower one of the threshold voltages VT2 and VT3 of the input gates 2 and 3, VT3 in the present example, the outputs of the input gates 3 and 9 are inverted, so the output of the input gate 9 becomes the ground potential GND. This, however, does not affect the outputs of the NOR gates 10 and 11. When the input signal voltage SIN further decreases and becomes lower than the threshold voltage VT2 of the input gate 2, the output of the input gate 2 becomes the supply potential VDD and the output of the NOR gate 10 becomes the ground potential GND, while the NOR gate 11 develops an output at the supply potential VDD.
As is understood from the above-described operation, when the input signal SIN rises, the inversion of the output signal SOUT occurs at the higher threshold voltage VT3, while it occurs at the lower threshold voltage VT2 when the input signal SIN falls. Like this, the conventional Schmitt trigger input buffer circuit shown in FIG. 1 has different threshold voltages VT2 and VT3 for the input gates 2 and 3 (e.g. VT2&lt;VT3), which provides the output signal SOUT with a hysteresis characteristic relative to the input signal SIN and, thus, provides a desired wave shaping function.
Because the hysteresis characteristic is determined by properly setting the operating threshold voltages of the two input gates, the adjustment of the hysteresis characteristic is easy, and the input impedance of this Schmitt trigger input buffer circuit can be chosen as desired.
However, the conventional Schmitt trigger input buffer circuit shown in FIG. 1 has a disadvantage because the R-S flip-flop circuit 30 is subject to external noise, such as noise contained in the input signal and noise undesirably introduced into it from power supply circuitry, it could operate erroneously.
For instance, let it be assumed that the input signal SIN slowly falls from the supply potential VDD toward the ground potential GND. When the input signal SIN decreases and crosses VT2, the output of the input gate 2 gradually increases toward the supply potential VDD. As explained above, in this condition, changes of the outputs of the NOR gates 10 and 11 are dependent on changes of the output of the input gate 2. Accordingly, when the potential at the input terminal 10a comes to have a value close to the threshold voltage of the NOR gate 10 as the output of the input gate 2 increases, the outputs of the NOR gates 10 and 11 change accordingly so that the other input terminal 10b of the gate 10 also receives a voltage near the threshold of the NOR gate 10.
This condition, however, is an unstable condition in which the output has not yet been changed completely. Therefore, if noise is applied through the input line, the power supply circuit or the like under this unstable condition, it is highly probable that the R-S flip-flop circuit 30 may operate erroneously in response to such noise.
Furthermore, if this Schmitt trigger input buffer circuit is formed as a CMOS circuit, unstable operating periods may occur because of an operating speed of P-channel MOSFET's which is slower than that of N-channel MOSFET's, and, therefore, if noise is applied during such unstable operating periods, the circuit may operate erroneously.
The third type of Schmitt trigger input buffer circuit which employs a R-S flip-flop comprising NAND gates is shown, for example, in FIGS. 7, 1 and 5 of Japanese Unexamined Patent Publication No. SHO 62-292014. This type of circuit includes a pair of dual-input NAND gates. One input of each of the NAND gates is coupled to the output of the other NAND gate, and anti-phased inputs are applied to the other inputs through appropriate input gates, such as inverters and NAND gates. Anti-phased outputs are derived from the pair of NAND gates. As in the case of the above-described second type of Schmitt trigger input buffer circuit, the adjustment of the hysteresis characteristic is relatively easy and an appropriate value of the input impedance can be obtained in this third type, too. However, it is impossible to prevent this circuit from being subject to erroneous operation caused by noise, too.
The fourth type of Schmitt trigger input buffer circuit which uses three or more NAND gates is shown, for example, in FIG. 4 of Japanese Unexamined Patent Publication No. SHO 61-223671 published on Oct. 4, 1987. This circuit includes first and second dual-input NAND gates. An input signal is applied to one of inputs of each NAND gates. The outputs of the two NAND gates are applied to first and second inputs of a third dual-input NAND gate, respectively. The output of the third NAND gate is coupled back to the other input of the second NAND gate. The two inputs of the first NAND gate are coupled together.
Adjustment of the hysteresis characteristic of this circuit is relatively easy, but the circuit tends to erroneously operate in response to noise.